Class CIM_PCIBridge
extends CIM_PCIController

Capabilities and management of a PCI controller providing bridge to bridge capability.

Class Hierarchy

CIM_ManagedElement
   |
   +--CIM_ManagedSystemElement
   |
   +--CIM_LogicalElement
   |
   +--CIM_LogicalDevice
   |
   +--CIM_Controller
   |
   +--CIM_PCIController
   |
   +--CIM_PCIBridge

Direct Known Subclasses

None.

Class Qualifiers

NameData TypeValueScopeFlavors
DescriptionstringCapabilities and management of a PCI controller providing bridge to bridge capability.None TRANSLATABLE= true

Local Class Properties

NameData TypeQualifiers
NameData TypeValueScopeFlavors
BridgeTypeuint16
DescriptionstringThe type of bridge. Except for "Host" (value=0), the type of bridge is PCI to <value>. For type "Host", the device is a Host to PCI bridge.None TRANSLATABLE= true
ValueMapstring0, 1, 2, 3, 4, 5, 6, 7, 8, 128None None
ValuesstringHost, ISA, EISA, Micro Channel, PCI, PCMCIA, NuBus, CardBus, RACEway, OtherNone TRANSLATABLE= true
IOBaseuint8
DescriptionstringBase address of I/O addresses supported by the bus. The upper four bits of this property specify the address bits, AD[15::12], of the I/O address. The remaining 12 bits of the I/O address are assumed to be 0.None TRANSLATABLE= true
IOBaseUpper16uint16
DescriptionstringUpper 16 bits of the supported I/O base address when 32-bit I/O addressing is used. The lower 16 bits are assumed to be 0.None TRANSLATABLE= true
IOLimituint8
DescriptionstringEnd address of the I/O addresses supported by the bus. The upper four bits of this property specify the address bits, AD[15::12], of the I/O address. The remaining 12 bits of the I/O address are assumed to be all 1's.None TRANSLATABLE= true
IOLimitUpper16uint16
DescriptionstringUpper 16 bits of the supported I/O end address when 32-bit I/O addressing is used. The lower 16 bits are assumed to be all 1's.None TRANSLATABLE= true
MemoryBaseuint16
DescriptionstringBase address of the memory supported by the bus. The upper twelve bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. The remaining 20 bits of the address are assumed to be 0.None TRANSLATABLE= true
MemoryLimituint16
DescriptionstringEnd address of the memory supported by the bus. The upper twelve bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. The remaining 20 bits of the address are assumed to be all 1's.None TRANSLATABLE= true
PrefetchBaseUpper32uint32
DescriptionstringUpper 32 bits of the supported prefetch base address when 64-bit addressing is used. The lower 32 bits are assumed to be 0.None TRANSLATABLE= true
PrefetchLimitUpper32uint32
DescriptionstringUpper 32 bits of the supported prefetch end address when 64-bit addressing is used. The lower 32 bits are assumed to be all 1's.None TRANSLATABLE= true
PrefetchMemoryBaseuint16
DescriptionstringBase address of the memory that can be prefetched by the bus. The upper twelve bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. The remaining 20 bits of the address are assumed to be 0.None TRANSLATABLE= true
PrefetchMemoryLimituint16
DescriptionstringEnd address of the memory that can be prefetched by the bus. The upper twelve bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. The remaining 20 bits of the address are assumed to be all 1's.None TRANSLATABLE= true
PrimaryBusNumberuint8
DescriptionstringThe number of the PCI bus segment to which the primary interface of the bridge is connected.None TRANSLATABLE= true
SecondaryBusDeviceSelectTiminguint16
DescriptionstringThe slowest device select timing for a target device on the secondary bus.None TRANSLATABLE= true
ValuesstringUnknown, Other, Fast, Medium, Slow, ReservedNone TRANSLATABLE= true
SecondaryLatencyTimeruint8
DescriptionstringThe timeslice for the secondary interface when the bridge is acting as an initiator. A zero value indicates no requirement.None TRANSLATABLE= true
UnitsstringPCI clock cyclesNone TRANSLATABLE= true
SecondaryStatusRegisteruint16
DescriptionstringThe contents of the Bridge's SecondaryStatusRegister. For more information on the contents of this register, refer to the PCI-to-PCI Bridge Architecture Specification.None TRANSLATABLE= true
SecondayBusNumberuint8
DescriptionstringThe number of the PCI bus segment to which the secondary interface of the bridge is connected.None TRANSLATABLE= true
SubordinateBusNumberuint8
DescriptionstringThe number of the highest numbered bus that exists behind the bridge.None TRANSLATABLE= true

Inherited Properties

NameData TypeClass Origin
Availabilityuint16CIM_LogicalDevice
CacheLineSizeuint8CIM_PCIController
CaptionstringCIM_ManagedElement
ClassCodeuint8CIM_PCIController
CommandRegisteruint16CIM_PCIController
CreationClassNamestringCIM_LogicalDevice
DescriptionstringCIM_ManagedElement
DeviceIDstringCIM_LogicalDevice
DeviceSelectTiminguint16CIM_PCIController
ErrorClearedbooleanCIM_LogicalDevice
ErrorDescriptionstringCIM_LogicalDevice
ExpansionROMBaseAddressuint32CIM_PCIController
InstallDatedatetimeCIM_ManagedSystemElement
InterruptPinuint16CIM_PCIController
LastErrorCodeuint32CIM_LogicalDevice
LatencyTimeruint8CIM_PCIController
MaxNumberControlleduint32CIM_Controller
MaxQuiesceTimeuint64CIM_LogicalDevice
NamestringCIM_ManagedSystemElement
PowerManagementSupportedbooleanCIM_LogicalDevice
PowerOnHoursuint64CIM_LogicalDevice
ProtocolDescriptionstringCIM_Controller
ProtocolSupporteduint16CIM_Controller
SelfTestEnabledbooleanCIM_PCIController
StatusstringCIM_ManagedSystemElement
StatusInfouint16CIM_LogicalDevice
SystemCreationClassNamestringCIM_LogicalDevice
SystemNamestringCIM_LogicalDevice
TimeOfLastResetdatetimeCIM_Controller
TotalPowerOnHoursuint64CIM_LogicalDevice